Design of a Clock and Data Recovery Circuit Using the Multi-point Phase Detector
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چکیده
منابع مشابه
A CMOS Clock and Data Recovery Circuit with a Half-Rate Three-State Phase Detector
A clock and data recovery (CDR) circuit using a new halfrate wide-range phase detection technique has been developed. Unlike the conventional three-state phase detectors, the proposed detector is applicable to the Non-Return-to-Zero (NRZ) data stream and also has low jitter and wide capture range characteristics. The CDR circuit was implemented in a 0.35-μm N-well CMOS technique. Experimental r...
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* This work was supported, in part, by Texas Instruments Inc., RocketChips Inc. and the R. J. Carver trust. Abstract – The Phase-Locked Loop (PLL) is a widely used block in data and clock recovery circuits. Phase detectors form a crucial part of the PLL. The requirements for phase detectors used in random data recovery are more stringent than the one used for clock recovery, especially at highs...
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ژورنال
عنوان ژورنال: The Journal of the Korea Contents Association
سال: 2010
ISSN: 1598-4877
DOI: 10.5392/jkca.2010.10.2.072